🚀 go-pugleaf

ellis@ultra.dec.com (David Ellis 15-Nov-1990 0915) writes:
>If we use a single .c.o rule for compiling all the source files, then it 
>seems that a change in a .h file that is #include'd in a .c file will
>not be picked up by Make to automatically force recompilation of the .c file.

>One workaround is to replace the single .c.o rule with a collection of rules, 
>one for each .o file, listing the dependencies on the .h files #include'd in
>the corresponding .c file.  But this is a lot of writing, and if we change
>the "#include" lines in any .c file, we have to update the Makefile with the
>corresponding change.

>Is there a simpler way?

 I do the following to generate my entire makefile

note: I have all my .c files in c/ and all .h files in h/ and I put all
 objects in o/
note 2: I use awk excessively due to the lack of a better output
formatter

----------------------------------------
# Find the Source
echo SRC | awk '{printf("\n%s=    ",$1)}'
foreach i (c/*)
 echo $i | awk '{printf("\\\n\t\t\t%s  ", $1) }'
end

# The objects to compile,
echo OBJ | awk '{printf("\n\n%s=    ",$1)}'
foreach i (c/*)
 echo $i | awk '{printf("\\\n\t\t\to/%s.o  ", substr($1,3,length($1)-4))}'
end

# The make command, assuming flags and everything are defined already
echo " "
echo $all': $(OBJ)'
echo '$(CC) $(CFLAGS) $(OBJ) -o ' $all '$(LIB) -lm' | \
awk '{printf("\t%s\n",$0)}'
echo " "
echo '$(OBJ):'
echo '$(CC) $(CFLAGS) $(IDIR) -c -o o/$*.o c/$*.c' | \
awk '{printf("\t%s\n",$0)}'
echo " "


# Generate the dependencies, basically searches .c files for 
#  include statements. If the included files is in quotes,
#  it is a dependency, otherwise not.
egrep include c/* | sed -e "s/#/\ /g" -e s/\"/\ /g  |   \
awk 'BEGIN {src=" "} \
        {sn=substr($1,3,length($1)-5) } \
        {if (src!=$1)printf("\n\no/%s.o:\t\tc/%s.c", sn, sn) } \
        {src=$1} \
        {if (substr($3,1,1)!="<") printf("\t\\\n\t\t\th/%s\t\t",$3) }'

--------------------------
 
    Harjinder Sandhu
    hsandhu@white.toronto.edu
    
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