🚀 go-pugleaf

>---------------------------------------------------------
>"Creating Third Generation I/O Interconnect"
>
>Presenter:
>Ajay Bhatt
>Intel Distinguished Lecturer
>
>A SEMINAR jointly sponsored by the
>Colorado Center for Information Storage
>at the University of Colorado, Boulder
>and the Denver Chapter of the IEEE Magnetics Society
>
>DATE:
>Tuesday, November 12, 2002
>
>TIME:
>5:30 pm
>
>PLACE:
>Classroom ECCR 200 (second floor, classroom wing)
>College of Engineering
>University of Colorado, Boulder
>
>TITLE:
>Creating Third Generation I/O Interconnect
>
>SPEAKER:
>Ajay Bhatt
>Intel Distinguished Lecturer
>
>ABSTRACT:
>During the past decade, PCI has been a very successful, general purpose I/O
>interconnect standard in the computing industry. However, demands of
>emerging and future computing models will exceed the bandwidth and
>scalability limits that are inherent in multi-drop, parallel bus
>implementations. Technologies such as CPU speeds that will exceed 10 GHz,
>faster memory speeds, higher-speed graphics, 1 Gigabit and 10 Gigabit LAN,
>1394b, InfiniBand* fabrics and others will drive the need for much greater
>internal bandwidth.
>
>The 3rd Generation I/O interconnect is defined to be scaleable to ~10Gb/S,
>limits of copper, while remaining backwards compatible with existing PCI
>software. The Creating 3rd Generation I/O Interconnect talk will provide an
>overview of Architecture and Technology for a highly scalable, high
>performance and cost-effective general purpose I/O solution for the next
>decade. The talk will also cover application of the 3GIO technology in
>emerging Client PCs, Servers and Communication devices.
>
>BIOGRAPHY:
>Ajay Bhatt is the Principal Engineer for the Desktop Architecture Lab, a
>part of Intel's Desktop Products Group, in Oregon. Ajay directs several
>teams responsible for the long-term architecture and technology directions
>for Intel Architecture Platforms. His team's projects are typically 2 to 5
>years prior to product introduction and have included development of the
>architecture and specifications of key technologies for Intel Architecture
>Platforms. At Intel Ajay has lead definition and development of technologies
>such as the Universal Serial Bus (USB), Accelerated Graphics Port (AGP4X)
>and Architectural Chipset Enhancements for the desktops. Ajay is currently
>leading the development of the 3GIO architecture and specification.
>
>Ajay has a M.E. in Electrical Engineering from the City University of New
>York. He worked at Wang Laboratories until 1990 when he joined Intel. In
>1997, Ajay was nominated and took part in a Distinguished Lecture Series at
>leading Universities in the United States and Asia.
>
>OTHER INFORMATION:
>All are welcome - both IEEE members and non-members.  If you are not a
>member, please consider joining the IEEE Magnetics Society to help support
>events like this.  See http://www.ieeemagnetics.org for more information.
>
>The talk is free and open to all; reservations are not required.
>
>Refreshments provided by KnowledgeTek (http://knowledgetek.com).
>
>Directions and a map are available at http://ccis.colorado.edu -- click on
>"Seminars", then on "Directions."
>
>
>
>
>
>
>
>
>
>

_______________________________________________
cscolloq mailing list
cscolloq@cs.colorado.edu
http://www.cs.colorado.edu/mailman/listinfo/cscolloq