Re: Caught by cache?

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Article #68978

#68978

From: John Naismith
Date: Tue, 16 Apr 1996 00:00

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In article: <61gucDAfVUcxEw5c@mwb.u-net.com>  Marcus Bainbridge 
<marcus@mwb.u-net.com> writes:

> Crap.  The cache controller is built into the PCIset.  Write-back is a
> function of the cache controller, but it doesn't take two chips to
> implement it.  It does, however, take two SRAM chips to make 64-bit
> cache.  Or QFP mouldings in this case...

I've just checked & these chips have 128 pins on each. Seems a little excessive 
for 64 bit cache ? 

64 bit data + 32 bit address + ?

Anyone know what the hell they are?

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From: John Naismith <John@naismith.demon.co.uk>
Subject: Re: Caught by cache?
Date: 1996/04/16
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