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Article #68985Re: Caught by cache?
From: Marcus Bainbridge
Date: Tue, 16 Apr 1996 00:00
Date: Tue, 16 Apr 1996 00:00
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1552 bytes
John Naismith <John@naismith.demon.co.uk> wrote: >I've just checked & these chips have 128 pins on each. Seems a little excessive >for 64 bit cache ? > >64 bit data + 32 bit address + ? > >Anyone know what the hell they are? Well, if you have a part number... :-> With QFP and similar devices, they come in standard pin arrays, so there could be a lot of power pins (ISTR something about quad cache having a particular problem with routing power around the silicon..?) But if they are cache controllers, then then have to access 64-bit data and 20-bit cache address (say), plus chip selects, interfaces with main memory (could be on a different bus and multiplexed by the cache controller, so call it another 64-bit data and 32-bit DRAM address). All adds up... If I could find the manual for my motherboard (never trust a woman to tidy up - you'll never find anything ever again...), I could find out a bit more about the Triton chipset. Maybe it's on the Intel CDs at work..? -- Marcus Bainbridge marcus@mwb.u-net.com - http://www.geocities.com/SunsetStrip/3429
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X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: 1036bc,7858595a79b6a65d X-Google-Attributes: gid1036bc,public From: Marcus Bainbridge <marcus@mwb.u-net.com> Subject: Re: Caught by cache? Date: 1996/04/16 Message-ID: <oKMISAAuP+cxEwZ2@mwb.u-net.com> X-Deja-AN: 148265390 distribution: world references: <415183800wnr@draycot.demon.co.uk> organization: Sweeping Generalisations Inc. mime-version: 1.0 newsgroups: demon.tech.pc