🚀 go-pugleaf

In article: <oKMISAAuP+cxEwZ2@mwb.u-net.com>  Marcus Bainbridge 
<marcus@mwb.u-net.com> writes:

> Well, if you have a part number... :->

I did - took it to work to check the number against the 1996 IC Master CD-ROM. 
Didn't recognise it. I didn't either, but since I mainly deal with military 
specced devices that's probably not surprising :)

I'll try opening the case this weekend to get the info.

> With QFP and similar devices, they come in standard pin arrays, so there
> could be a lot of power pins (ISTR something about quad cache having a
> particular problem with routing power around the silicon..?)

Yes, I'd expect 5-10 for Vcc & same for 0V. BTW, it's not routing that's such a 
problem, it's "hot spots" on the silicon that are a real bastard. If you want an 
extreme example the 60/66MHz Pentiums have upwards of 40 Vcc pins - and all this 
does is make the whole bloody thing hot :)
 
> But if they are cache controllers, then then have to access 64-bit data
> and 20-bit cache address (say), plus chip selects, interfaces with main
> memory (could be on a different bus and multiplexed by the cache
> controller, so call it another 64-bit data and 32-bit DRAM address).
> All adds up...

It does, doesn't it. But if the cache controller is in the PCISet (BTW, what 
does the L2 cache have to do with the PCI bus?), then what the hell are these?
I also remember seeing on the X-ray that a small number (5 (ish) ) of lines were 
absent from the die to the external pins.

These have the look of custom ASICs about them to me, but I'm now getting 
curious. Performance of the L1/L2 cache is about what I'd expect (L1=1GB/sec, 
L2=240MB/sec), but if I've been sold something "strange" then I'd like to know 
about it :)


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john@naismith.demon.co.uk
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