🚀 go-pugleaf

In article: <61gucDAfVUcxEw5c@mwb.u-net.com>  Marcus Bainbridge 
<marcus@mwb.u-net.com> writes:

> Crap.  The cache controller is built into the PCIset.  Write-back is a
> function of the cache controller, but it doesn't take two chips to
> implement it.  It does, however, take two SRAM chips to make 64-bit
> cache.  Or QFP mouldings in this case...

They're not mouldings on this board. Whatever they are there's silicon inside 
them as I've had the board in work & x-rayed it. They also get rather warm which 
is usually a good indication that something is dissipating heat & therefore 
drawing current (chips around them are cool). The board does not report cache as 
being fitted without a COAST module inserted. There are also a number of tracks 
going from these devices to the COAST socket which only have active signals on 
them when a module is present. Looked like address lines & strobes to me, but 
with the crap scope I've got at home (20MHz b/w) it's entirely possible that 
they're something else.

As you can probably tell I've looked into this quite closely as I got 
*seriously* paranoid when I saw chips labelled with "Write Back". While I don't 
have any info to contradict your assertion that the cache controller is in the 
PCISet I can assure you that the chips on my board are definately not fakes. If 
I knew who made it I'd post that, but (as happens too frequently) the board has 
no real identity marks on it & the manual gives no clues. It's a generic Triton 
chipset m/b supporting Pentiums up to 180MHz.
 

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john@naismith.demon.co.uk
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