Re: [Milkymist port] virtual memory management

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#124

From: Rhialto
Date: Wed, 29 May 2013 19:17

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On Wed 29 May 2013 at 19:51:15 +0200, Yann Sionneau wrote:
> 1�) some code somewhere generates an I(nstruction) TLB miss in the
> MMU, this leads to a CPU exception, CPU then branches immediately to
> the "ITLB miss" exception vector.

(Side issue I've been wondering about: Why does almost everybody these
days call their Address Translation Cache now Translation Lookaside
Buffer?  Why prefer vague IBM terminology over a clear Motorola term?)

To respond to your question: the easiest is probably to reserve a couple
of cache entries for essential must-never-trap code and data address
ranges.

-Olaf.
-- 
___ Olaf 'Rhialto' Seibert  -- The Doctor: No, 'eureka' is Greek for
\X/ rhialto/at/xs4all.nl    -- 'this bath is too hot.'

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From: Rhialto <rhialto@falu.nl>
Newsgroups: fa.netbsd.tech.kern
Subject: Re: [Milkymist port] virtual memory management
Date: Wed, 29 May 2013 19:17:55 UTC
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Cc: tech-kern@netbsd.org, devel@lists.milkymist.org,
        Radoslaw Kujawa <radoslaw.kujawa@c0ff33.net>
To: Yann Sionneau <yann.sionneau@gmail.com>
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