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               MulSim Multiprocessor Simulator

	             Norman S. Matloff
              University of California at Davis
	        Division of Computer Science
	       matloff@heather.cs.ucdavis.edu
		      (916) 752-1953


     MulSim simulates the operation of a shared-memory multiprocessor
system.  Its processor type is of a RISC design largely similar to
the SPARC architecture  --  i.e. instructions execute in a single cycle, 
and it is a load/store machine, with all arithmetic operations being done 
in register-to-register mode only  --  with a system of register windows 
being used to store the runtime stack.  User programs are written in 
the assembly language for this architecture.

     The user may choose from several types of processor/memory 
interconnects, or may develop his/her own type of interconnect; MulSim 
has been designed in a modular fashion which facilitates the user taking 
the latter approach.  There are also optional features which allow the 
user to do statistics-gathering, etc.

     The system includes a fairly extensive debugging facility, which
can be used not only for debugging but also for close examination of
program behavior, e.g. to help identify how memory contention problems
arise.

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               The MulSim system is available free of charge 
	       for noncommercial use, e.g. in universities. 
	       To obtain a copy, please send e-mail to 

		      matloff@heather.cs.ucdavis.edu

	       Be sure to specify the type(s) of host machine 
	       you wish to run MulSim on (presently it is
	       available for SPARCstation, DECstation and DOS 
	       systems).