Article View: fj.sys.pc98
Article #282How to 286 -> 386sx (486slc)
From: Haruhiko Kuroe
Date: Wed, 26 Aug 1992 17:06
Date: Wed, 26 Aug 1992 17:06
130 lines
6808 bytes
6808 bytes
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BHE# Value A0 Value
0 0 Word transfer
0 1 Byte transfer on upper half of data (D15-D8)
1 0 Byte transfer on lower half of data (D7-D0)
1 1 Will never occer
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BHE#,BLE# Byte Enables indicate which data bytes of the data bus
in a bus cycle.
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COD/INTA# M/IO# S1# S0# Bus Cycle Initiated
0 0 0 0 Interrupt acknowledge
0 0 0 1 Will not occur
0 0 1 0 Will not occur
0 0 1 1 None;not a status cycle
0 1 0 0 IF A1=1 then halt;else shutdown
0 1 0 1 Memory data read
0 1 1 0 Memory data write
0 1 1 1 None;not a status cycle
1 0 0 0 Will not occur
1 0 0 1 I/O read
1 0 1 0 I/O write
1 0 1 1 None;not a status cycle
1 1 0 0 Will not occur
1 1 0 1 Memory instruction read
1 1 1 0 Will not occur
1 1 1 1 None;not a status cycle
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M/IO# Memory/IO is a bus cycle definition pin that distingishes
memory cycles from input/output cycles.
W/R# Write/Read is a bus cycle definition pin that distingishes
write cycles from read cycles.
D/C# Data/Control is a bus cycle definition pin that
distinguishes data cycles, either memory or I/O, from
control cycles which are interrupt acknowledge, halt, and
code fetch.
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Technical Details
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Path: arc1-ca.pugleaf.net!sparky!uunet!sun-barr!sh.wide!wnoc-tyo-news!hoffman!h-kuroe@hoffman.cc.sophia.ac.jp From: h-kuroe@hoffman.cc.sophia.ac.jp (Haruhiko Kuroe) Newsgroups: fj.sys.pc98 Subject: How to 286 -> 386sx (486slc) Message-ID: <4879@hoffman.cc.sophia.ac.jp> Date: 26 Aug 92 17:06:16 GMT Sender: news@hoffman.cc.sophia.ac.jp Distribution: fj Organization: Computer Center, Sophia Univ., Tokyo, Japan Lines: 130