🚀 go-pugleaf

The following suggestion allows something useful to be done 
with a bit field produced by a signed extraction compared against zero.

The RTL pattern

    (set (reg:SI n)
         (ashiftrt:SI (ashift (reg:SI)     ;; from a bit field extraction
                              (const_int))
                      (const_int)))
    (set (cc0)
         (compare (reg:SI n)
                  (const_int 0)))

was being munged by `simplify_condition()' into 

   (set (cc0)
        (subreg:BLK (reg:SI n) 0))

by adding the line denoted by /* WRA */ in the following 
test in `simplify_condition()'

       case ASHIFTRT:
	  /* If OP0 is a sign extension and CODE is not an unsigned comparison,
	     do the comparison in a narrower mode.  */
	  if (! unsigned_comparison_p
	      && GET_CODE (XEXP (op0, 1)) == CONST_INT
	      && GET_CODE (XEXP (op0, 0)) == ASHIFT
	      && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
	      && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
					 MODE_INT, 1)) != VOIDmode
/* WRA */     && tmode != BLKmode  
	      && ((unsigned) const_op <= GET_MODE_MASK (tmode)
		  || (unsigned) - const_op <= GET_MODE_MASK (tmode)))
	    {
	      op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
	      continue;
	    }

the RTL was reduced to the "correct" zero_extraction pattern.

    (set (cc0)
         (zero_extract (reg:SI n) ..))
                       
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	     ___________     William Athanasiou, Software Engineer
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	   /__/_______/  /   will@westford.ccur.com
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