🚀 go-pugleaf

Machine: 1750-A (I'm doing the port). This is a 16 bit word adressable  
machine; all memory and registers are 16 bits. HI mode is 32 bits (2  
registers).

I have a reload problem. Although the code says that it tries to spill groups  
first, I've got one case where it is spilling a single register first (from a  
different class), and then it later spills a LOWER register to join the first  
register as a group; except that the register order specifies using the higher  
register first. Since it is also spilling the two registers immediately after  
it, this assignment works, but results in breaking up the group.

In other words: First spill R6 for a single for register class 5. Then spill  
two groups, one R5-R6, one R7-R8, for class 6. At allocation time, use R6-R7,  
and then be unable to spill R5 and R8.
(the fatal insn does not need r5 as a single register, it just needs two  
groups of 2)

With round robin allocation disabled (workaround for another problem):

(146) % cc1 temp.i
 convert_for_assignmentCalling order_reg's
spilling hard reg 14
Spilling for class 0
Maxgroups[class] is 0
Looking for single registers; maxneeds, maxnongroups are 0, 0
Spilling for class 1
Maxgroups[class] is 0
Looking for single registers; maxneeds, maxnongroups are 0, 0
Spilling for class 2
Maxgroups[class] is 0
Looking for single registers; maxneeds, maxnongroups are 0, 0
Spilling for class 3
Maxgroups[class] is 0
Looking for single registers; maxneeds, maxnongroups are 0, 0
Spilling for class 4
Maxgroups[class] is 0
Looking for single registers; maxneeds, maxnongroups are 0, 0
Spilling for class 5
Maxgroups[class] is 0
Looking for single registers; maxneeds, maxnongroups are 1, 0
Called to spill i 0, reg 6, nspills 0
spilling hard reg 6
Found an overlap
Actually changed i, reg 27
Spilling for class 6
Maxgroups[class] is 2
Calling new_spill_reg for 2 5
Called to spill i 2, reg 5, nspills 1
spilling hard reg 5
Found an overlap
Actually changed i, reg 20
Calling new_spill_reg for 3 7
Called to spill i 3, reg 7, nspills 2
spilling hard reg 7
Found an overlap
Actually changed i, reg 28
Calling new_spill_reg for 4 8
Called to spill i 4, reg 8, nspills 3
spilling hard reg 8
Looking for single registers; maxneeds, maxnongroups are -2, 0
Spilling...
Spilling for class 0
Maxgroups[class] is 0
Looking for single registers; maxneeds, maxnongroups are 0, 0
Spilling for class 1
Maxgroups[class] is 0
Looking for single registers; maxneeds, maxnongroups are 0, 0
Spilling for class 2
Maxgroups[class] is 0
Looking for single registers; maxneeds, maxnongroups are 0, 0
Spilling for class 3
Maxgroups[class] is 0
Looking for single registers; maxneeds, maxnongroups are 0, 0
Spilling for class 4
Maxgroups[class] is 0
Looking for single registers; maxneeds, maxnongroups are 0, 0
Spilling for class 5
Maxgroups[class] is 0
Looking for single registers; maxneeds, maxnongroups are 1, 0
Called to spill i 0, reg 6, nspills 0
spilling hard reg 6
Spilling for class 6
Maxgroups[class] is 2
Calling new_spill_reg for 1 5
Called to spill i 1, reg 5, nspills 1
spilling hard reg 5
Calling new_spill_reg for 2 7
Called to spill i 2, reg 7, nspills 2
spilling hard reg 7
Calling new_spill_reg for 3 8
Called to spill i 3, reg 8, nspills 3
spilling hard reg 8
Looking for single registers; maxneeds, maxnongroups are -2, 0
Spilling regs 6 5 7 8
looking at reload order 0
Spilling regs 6 5 7 8
looking at reload order 0
Spill reset
Allocate called. Last 0, n_spills 4, used 0, nongroups 0, nr 1
last_spill updated to 0
looking at reload order 1
Allocate called. Last 0, n_spills 4, used 40, nongroups 0, nr 1
last_spill updated to 1
Spilling regs 6 5 7 8
looking at reload order 0
Allocate called. Last 1, n_spills 4, used 0, nongroups 0, nr 1
last_spill updated to 0
Spilling regs 6 5 7 8
looking at reload order 0
Spilling regs 6 5 7 8
looking at reload order 0
Allocate called. Last 0, n_spills 4, used 0, nongroups 0, nr 1
last_spill updated to 0
looking at reload order 1
Allocate called. Last 0, n_spills 4, used 40, nongroups 0, nr 1
last_spill updated to 1
Spilling regs 6 5 7 8
looking at reload order 0
Spilling regs 6 5 7 8
looking at reload order 0
Allocate called. Last 1, n_spills 4, used 0, nongroups 0, nr 1
last_spill updated to 0
looking at reload order 1
Allocate called. Last 0, n_spills 4, used 40, nongroups 0, nr 1
last_spill updated to 1
Spilling regs 6 5 7 8
looking at reload order 0
Spilling regs 6 5 7 8
looking at reload order 0
Allocate called. Last 1, n_spills 4, used 0, nongroups 0, nr 1
last_spill updated to 0
looking at reload order 1
Allocate called. Last 0, n_spills 4, used 40, nongroups 0, nr 1
last_spill updated to 1
Spilling regs 6 5 7 8
looking at reload order 0
Spilling regs 6 5 7 8
looking at reload order 0
Allocate called. Last 1, n_spills 4, used 0, nongroups 0, nr 1
last_spill updated to 0
Spilling regs 6 5 7 8
looking at reload order 0
Allocate called. Last 0, n_spills 4, used 0, nongroups 0, nr 1
last_spill updated to 0
Spilling regs 6 5 7 8
looking at reload order 0
Allocate called. Last 0, n_spills 4, used 0, nongroups 0, nr 2
last_spill updated to 0
looking at reload order 1
Allocate called. Last 0, n_spills 4, used c0, nongroups 0, nr 2
last_spill updated to 0
looking at reload order 2
Allocate called. Last 0, n_spills 4, used c0, nongroups 0, nr 2
No reg found
Abort called.
IOT trap
3.5u 0.5s 0:14 27% 0+0k 118+4io 0pf+0w
(147) %

With round robin allocation enabled (normal):

(149) % cc1 temp.i
 convert_for_assignmentCalling order_reg's
spilling hard reg 14
Spilling for class 0
Maxgroups[class] is 0
Looking for single registers; maxneeds, maxnongroups are 0, 0
Spilling for class 1
Maxgroups[class] is 0
Looking for single registers; maxneeds, maxnongroups are 0, 0
Spilling for class 2
Maxgroups[class] is 0
Looking for single registers; maxneeds, maxnongroups are 0, 0
Spilling for class 3
Maxgroups[class] is 0
Looking for single registers; maxneeds, maxnongroups are 0, 0
Spilling for class 4
Maxgroups[class] is 0
Looking for single registers; maxneeds, maxnongroups are 0, 0
Spilling for class 5
Maxgroups[class] is 0
Looking for single registers; maxneeds, maxnongroups are 1, 0
Called to spill i 0, reg 6, nspills 0
spilling hard reg 6
Found an overlap
Actually changed i, reg 27
Spilling for class 6
Maxgroups[class] is 2
Calling new_spill_reg for 2 5
Called to spill i 2, reg 5, nspills 1
spilling hard reg 5
Found an overlap
Actually changed i, reg 20
Calling new_spill_reg for 3 7
Called to spill i 3, reg 7, nspills 2
spilling hard reg 7
Found an overlap
Actually changed i, reg 28
Calling new_spill_reg for 4 8
Called to spill i 4, reg 8, nspills 3
spilling hard reg 8
Looking for single registers; maxneeds, maxnongroups are -2, 0
Spilling...
Spilling for class 0
Maxgroups[class] is 0
Looking for single registers; maxneeds, maxnongroups are 0, 0
Spilling for class 1
Maxgroups[class] is 0
Looking for single registers; maxneeds, maxnongroups are 0, 0
Spilling for class 2
Maxgroups[class] is 0
Looking for single registers; maxneeds, maxnongroups are 0, 0
Spilling for class 3
Maxgroups[class] is 0
Looking for single registers; maxneeds, maxnongroups are 0, 0
Spilling for class 4
Maxgroups[class] is 0
Looking for single registers; maxneeds, maxnongroups are 0, 0
Spilling for class 5
Maxgroups[class] is 0
Looking for single registers; maxneeds, maxnongroups are 1, 0
Called to spill i 0, reg 6, nspills 0
spilling hard reg 6
Spilling for class 6
Maxgroups[class] is 2
Calling new_spill_reg for 1 5
Called to spill i 1, reg 5, nspills 1
spilling hard reg 5
Calling new_spill_reg for 2 7
Called to spill i 2, reg 7, nspills 2
spilling hard reg 7
Calling new_spill_reg for 3 8
Called to spill i 3, reg 8, nspills 3
spilling hard reg 8
Looking for single registers; maxneeds, maxnongroups are -2, 0
Spilling regs 6 5 7 8
looking at reload order 0
Spilling regs 6 5 7 8
looking at reload order 0
Allocate called. Last 0, n_spills 4, used 0, nongroups 0, nr 1
last_spill updated to 0
looking at reload order 1
Allocate called. Last 0, n_spills 4, used 40, nongroups 0, nr 1
last_spill updated to 1
Spilling regs 6 5 7 8
looking at reload order 0
Allocate called. Last 1, n_spills 4, used 0, nongroups 0, nr 1
last_spill updated to 1
Spilling regs 6 5 7 8
looking at reload order 0
Spilling regs 6 5 7 8
looking at reload order 0
Allocate called. Last 1, n_spills 4, used 0, nongroups 0, nr 1
last_spill updated to 1
looking at reload order 1
Allocate called. Last 1, n_spills 4, used 20, nongroups 0, nr 1
last_spill updated to 2
Spilling regs 6 5 7 8
looking at reload order 0
Spilling regs 6 5 7 8
looking at reload order 0
Allocate called. Last 2, n_spills 4, used 0, nongroups 0, nr 1
last_spill updated to 2
looking at reload order 1
Allocate called. Last 2, n_spills 4, used 80, nongroups 0, nr 1
last_spill updated to 3
Spilling regs 6 5 7 8
looking at reload order 0
Spilling regs 6 5 7 8
looking at reload order 0
Allocate called. Last 3, n_spills 4, used 0, nongroups 0, nr 1
last_spill updated to 3
looking at reload order 1
Allocate called. Last 3, n_spills 4, used 100, nongroups 0, nr 1
last_spill updated to 0
Spilling regs 6 5 7 8
looking at reload order 0
Spilling regs 6 5 7 8
looking at reload order 0
Allocate called. Last 0, n_spills 4, used 0, nongroups 0, nr 1
last_spill updated to 0
Spilling regs 6 5 7 8
looking at reload order 0
Allocate called. Last 0, n_spills 4, used 0, nongroups 0, nr 1
last_spill updated to 0
Spilling regs 6 5 7 8
looking at reload order 0
Allocate called. Last 0, n_spills 4, used 0, nongroups 0, nr 2
last_spill updated to 0
looking at reload order 1
Allocate called. Last 0, n_spills 4, used c0, nongroups 0, nr 2
last_spill updated to 0
looking at reload order 2
Allocate called. Last 0, n_spills 4, used c0, nongroups 0, nr 2
No reg found
Abort called.
IOT trap
3.6u 0.4s 0:14 29% 0+0k 117+4io 0pf+0w
(150) %

Class 5 and 6 are as follows:
#define REG_CLASS_CONTENTS \
{                                       \
        0x0,            /* No */        \
        0x0004, /* R2           */      \
        0x0003, /* R01          */      \
        0x8000, /* stack        */      \
        0xF000, /* Index */             \
        0xFFFE, /* base or index */     \
        0xFFFF, /* all */               \
}

Class 5 is everything but R0, class 6 is everything

Test case is "convert_for_assignment". Machine is the 1750-A, a 16 bit word  
machine that requires most operations to be done in 32 bit mode to avoid  
hardware overflow. (QI is 16 bits, HI is 32. Fun.)

Possible ways to fix, that I can see (will these break something else?):
1. Re-order the entries in spill_reg_order to be incremental.
2. Do all groups for all classes, and then the singles for all classes,  
instead of doing the singles for one class before the groups for another  
class.

The insn that it is trying to work on is

No reg found

Bpt 1, 0xc270a in fancy_abort () (aux-output.c line 798)
798     {
(gdb) up
#1  0xb3ede in allocate_reload_reg (r=2, insn=(rtx) 0x26bb8a, last_reload=1,  
noerror=0) (reload1.c line 4236)
4236        abort ();
(gdb) p debug_rtx(insn)
(insn:HI 83 82 84 (parallel[
           (set (cc0)
               (compare (reg/v:HI 28)
                   (reg:HI 0 R0)))
           (clobber (scratch:HI))
           (clobber (scratch:HI))
       ] ) 39 {cmphi} (nil)
   (nil))

(the scratch reg's are needed to do an unsigned compare on this machine).

If you have any questions (such as the md file, the tm file, exactly where the  
printf's are, etc), let me know and I'll tell you.
--
	Michael Gersten		michael@stb.info.com
NeXT Registered Developer (NeRD) # 3860 -- Hire me! Quick!
Will program computers for food (and net connection, health benefits, cash,...)