🚀 go-pugleaf

I am trying to add a feature to a custom gcc-mips compiler to try 
to optimize for placement of branch instructions in an even word 
boundary address.
 
0x00020000      even instruction  word boundary:  (addr&4) == 0
0x00020004      odd instruction   word boundary:  (addr&4) == 1
0x00020008      even instruction  word boundary:  (addr&4) == 0

The processor is a 2 pipeline super-scalar architecture that 
benefits from a branch instruction in an even word address by
being able to displatch the instruction following, i.e. in
the branch delay slot in the same cycle.
 
Any thoughts on whether this is possible to describe in the
machine description file language?  Any similar cases
around for other processors?

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