🚀 go-pugleaf

While a pragma would be a nice idea.. There are a lot of times
that the compiler should be able to determine (or at least make a
good guess) if a conditional branch will be taken more often than
not. 

For instance, loops with constant limits (for (i=0;i <10;i++))
would be a prime example of where a pragma shouldn't be needed.
The optimizer should provide enough information to allow the
MD file to choose between branches that win on fall through, or
taken.

On machines like the i860, where branch delay slots are useful
only if the branch is taken more often than not, this type of
information would be a huge win!  Is there a way to even
determine the direction of the branch (up or down the instruction
stream.)? 

I think the loop optimization code could use some improvements in
other areas as well.  More and more, chips are coming out with
`repeat block' instructions.  For example the TI C40 chip has a
repeat instruction n times, as well as a repeat block n times
instruction.  I think the powerPC has one as well (somebody
correct me if I'm wrong).  Right now, it would be very hard to
write a pattern for those instructions. 

In effect, the DBRA instruction on the 680x0 processors is a
repeat block instruction as well.  Even the BLA instruction on
the I860 could be used as a repeat block instruction, if enough
information was known about the contents of the loop (no function
calls, no other BLA loops...). 

Maybe what is needed is a new type of loop_block pattern, with a
sequence of instructions as one of its arguments. 

Just a thought..

Will.

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