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Article #51096generating load/store at rtl level for sparc
From: Elliot Stewart
Date: Wed, 30 Jun 1993 21:24
Date: Wed, 30 Jun 1993 21:24
23 lines
1630 bytes
1630 bytes
I am using gcc v2.4.3 on the sun sparc. I am trying to generate a load and
a store instruction at the rtl level which will be inserted into a user
program. I have tried the following without success:
rtx _reg = gen_reg_rtx(SImode);
rtx _mem = gen_rtx(MEM, SImode, gen_rtx(SYMBOL_REF, SImode, "_count"));
.
.
pattern = gen_move_insn(_reg, validize_mem(_mem));
emit_insn_before(pattern, label_insn);
.
.
I have also tried using emit_move_insn and gen_movsi without correct results.
Sometimes I get the error "instruction not recognizable" or the instruction
is accepted but the program will core dump. Using adb I see that the dump is
caused by not performing the "correct two instruction steps" for a load in a
risc architecture (i.e. it doesnt load from the proper address).
If anyone can help me with this problem, please email.
Elliot Stewart
stewart@crhc.uiuc.edu
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X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: 11318c,7ba44594d9fcab23,start X-Google-Attributes: gid11318c,public X-Google-ArrivalTime: 1993-06-30 14:32:54 PST Path: arc1-ca.pugleaf.net!gmd.de!xlink.net!howland.reston.ans.net!ux1.cso.uiuc.edu!roundup.crhc.uiuc.edu!gershwin.crhc.uiuc.edu!not-for-mail From: stewart@crhc.uiuc.edu (Elliot Stewart) Newsgroups: gnu.gcc.help Subject: generating load/store at rtl level for sparc Date: 30 Jun 1993 16:24:50 -0500 Organization: Center for Reliable and High-Performance Computing, University of Illinois at Urbana-Champaign Lines: 23 Message-ID: <20t0b2INNnf1@gershwin.crhc.uiuc.edu> NNTP-Posting-Host: gershwin.crhc.uiuc.edu