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Article #51533Re: gcc suggestion
From: John F Carr
Date: Sat, 01 May 1993 23:15
Date: Sat, 01 May 1993 23:15
24 lines
1690 bytes
1690 bytes
In article <1993May1.192516.15296@uvm.edu>
wollman@sadye.emba.uvm.edu (Garrett Wollman) writes:
>For this particular situation, it would be nice if GCC had a
>`-funsigned-preserving' switch. (A `-muse-halfword-ops' switch would
>be nice, too.)
There's a macro in the machine description which may help, but I'm not sure
if it was in 2.3 (it will be in 2.4).
Try adding this to i386.h. It should cause gcc to use fewer halfword
operations on a 486.
#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
if (TARGET_486 && (MODE) == HImode) (MODE) = SImode
This macro is intended for RISC machines which don't have instructions that
operate on objects smaller than a word. The example above would make gcc use
32 bit registers and operations to hold 16 bit automatic variables. (This is
done so as not to change results; a short still can not exceed 2^16.)
--
John Carr (jfc@athena.mit.edu)
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X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: 11318c,e4b251dc276f69b7 X-Google-Attributes: gid11318c,public X-Google-Thread: 1025b4,e4b251dc276f69b7 X-Google-Attributes: gid1025b4,public X-Google-ArrivalTime: 1993-05-01 16:18:32 PST Path: arc1-ca.pugleaf.net!gmd.de!newsserver.jvnc.net!howland.reston.ans.net!noc.near.net!uunet!think.com!enterpoop.mit.edu!senator-bedfellow.mit.edu!athena.mit.edu!jfc From: jfc@athena.mit.edu (John F Carr) Newsgroups: gnu.gcc.help,gnu.misc.discuss Subject: Re: gcc suggestion Date: 1 May 1993 23:15:03 GMT Organization: Massachusetts Institute of Technology Lines: 24 Message-ID: <1rv09oINN7sa@senator-bedfellow.MIT.EDU> References: <1rs3rb$1bp@almaak.usc.edu> <1993May1.192516.15296@uvm.edu> NNTP-Posting-Host: achates.mit.edu