🚀 go-pugleaf

OK, here's the scoop.  I've been trying to create a compiler for a custom
processor which is based on the MIPS architecture but does not include byte (QI)
or half-word (HI) instructions.  My plan was to replace the movqi and movhi
insns with define_expands which would do the actual loads, shifting, and masking
required to implement the byte and half-word operations.  Unfortunately, these
insns are somewhat special - as noted on page 191 of the 2.1 docs - and I'll
be darned if I can get this to work.  I've tried several different approaches
but none have worked so far.

The main problem seems to be that since these insns are used after code 
generation (during reload) they cannot allocate temporary registers.  The
docs suggest looking at the spur.md file as an example.  I did this only to
find that this example (apparently) allocates several temporary registers.
I was confused by this apparent contradiction with the documentation but tried
applying the same approach.  Well, it seemed to work OK for the byte 
operations but failed for the HI insns.  Tracing back the problem revealed that
there is a check in the gen_reg_rtx() routine which aborts if called during
reload (reload_in_progress).  I tried removing this check (no, I didn't really
expect this to work) but this just caused problems further down the line.

So if anyone has followed this at all (or thinks they could offer assistance
given more information) please send email with any suggestions about what
I should do next.  In the meantime I'll keep plugging away at it.

					Thanks,
						Bob McVay
						mcvay@engin.umich.edu