🚀 go-pugleaf

			   Avant-Projet A3



Jeudi 22 fevrier 1996 a 14H		Pr. Guang R. Gao
INRIA Rocquencourt			Mc Gill University,
Salle de Conference du Bat. 16		Montreal


  
	Exploitation of Instruction Level Parallelism through
		 Hardware and Software Co-Scheduling

				Abstract


The effective  exploitation of instruction-level parallelism (ILP) for
the  development  of   the next-generation high-performance  computers
requires   the integrated development    of  compiler techniques   and
architectural design.  In  this talk, we  first outline major research
activities in  ILP  exploitation at  ACAPS, McGill.  Then,  as  a case
study,  we  present our  recent work on   developing a framework where
instruction level parallelism  is  exploited through a  combination of
techniques from both  software pipelining and hardware pipeline design
theory.  We demonstrate  that this software and hardware co-scheduling
framework  will  facilitate   the search of    the  best schedule  for
multiissue architectures with resource hazards.






Pour tous renseignements, s'adresser a :
	Christine Eisenbeis 
	tel : (1) 39 63 55 82 
	e-mail : christine.eisenbeis@inria.fr 

Comment se rendre a l'INRIA : http://www.inria.fr/Allera/Somm-aller-fra.html

Cette annonce  tient lieu de  laissez-passer  provisoire pour la  date
indiquee ci-dessus.

Possibilite de dejeuner sur place.