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                  COMPUTER ENGINEERING SEMINAR


                System Level Automatic Synthesis of Controllers
                     for High Speed ASIC Data Paths



                                   by


                            Fadi J. Kurdahi


             Electrical and Computer Engineering Department
                University Of California At Irvine



                                Abstract


We address the problem of control synthesis of pipelined data paths.
Two basic control schemes are possible: data-stationary and
time-stationary.  In this work, we consider the latter scheme.  We
developed an approach to automatically synthesize time-stationary
controllers for pipelined data paths which are produced by high level
synthesis tools such as Sehwa.  First a scheduled control/data flow
graph is analyzed and the various states are identified.  Overlapped
states are grouped together to produce $L$ groups where $L$ is the
pipeline initiation interval.  Next, state transitions are identified
and hence a state table is generated.  A highly optimized FSM
controller is then implemented by performing horizontal partitioning
and the corresponding state encoding so as to minimize the total
controller area.  Existing logic optimization programs (MIS and
ESPRESSO) are finally used to optimize the logic inside each partition
and generate PLA or standard cell implementations.  Experimental
results indicate that our methods result in large savings in total
controller area and tend to improve overall controller delay.






		 DATE:		 Friday, April 10, 1992

		 TIME:		 10:30 A.M. SEMINAR

		 LOCATION:	     EEB 248

		 HOST:		 Prof. Sandeep Gupta

				    (213)740-2251