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             COMPUTER ENGINEERING SEMINAR

           A Reconfigurable Processor Array 
      with Routing LSIs and General Purpose DSPs

                           by

                     Jacob Levison

         NEC C&C Systems Research Laboratories
                         Japan

                        Abstract

A building block for a scalable signal processor array is developed
with a general-purpose DSP and a message routing LSI.  Each DSP can be
connected by multiple routing LSIs forming a point-to-point
message-passing network with data packet communication. Low network
latency is obtained by cut-through routing technique with sufficient
communication bandwidth. The employment of an on-chip routing table
allows regular as well as irregular topologies with complex routing
techniques such as broad/multi-casting and dynamic routing. The
combination of DSPs (uPD77240), a flexible message-passing network and
an optional application-specific I/O interface makes the processor
array suitable for a wide range of high speed signal processing
applications such as adaptive array processing and 3-D vision
processing.

	DATE:	  WEDNESDAY, AUGUST 12, 1992

	TIME:	  10:30 A.M.: SEMINAR

		  11:30 A.M.: Q&A		

	LOCATION: ELECTRICAL ENGINEERING BUILDING 
                  (EEB 246)

	HOST:	  Prof. Viktor Prasanna
  		  213/ 740-4483