🚀 go-pugleaf

 The Interaction of Logical and Temporal Aspects of Circuit Behavior:
Issues in Analysis and Synthesis

                    Professor Sharad Malik
                     Princeton University

                           Abstract

 Static timing analysis is the most common approach to analyzing the
temporal behavior of combinational logic circuits. This is fast but
potentially inaccurate since it does not take into account the
functionality of the circuit components. It returns the length of the
longest path in the circuit, even though this path may never be
exercised in the actual operation of the circuit. Such paths are said
to be false. False path analysis (or functional timing analysis) has
seen a lot of work in recent years. I will present techniques for
functional timing analysis under a variety of assumptions for
the electrical behavior as well as component delays in the circuit.
Finally I will show how these results can be used in the synthesis
of high performance circuits.



              DATE:        Friday, November 13, 1992

              TIME:        10:30-12:00 

              LOCATION:    Seaver Science Auditorium

              HOST:        Dr. Massoud Pedram
                           213 740-4458