🚀 go-pugleaf

       Area Estimation in the PLAYOUT VLSI Design System



                      Bernd Schuermann
               University of Kaiserslautern
                           Germany

                           Abstract     



The estimation of the cell area before layout, especially of shape
functions, is very important in a hierarchical design process and a
necessity for top down design styles. It consists of two parts: the
computation of the overall subcell area and the estimation of the
wiring area of the channels between the subcells.

The major problem is the estimation of wiring space. For the internal
wiring between the subcells relative good models exist. Problems
occur for the wiring space to connect the subcells with the external
pins of a cell.

The talk gives a mathematical description of our wiring model and 
especially treats the pin connection problem. Our goal is to find the
simplest model that explains the experiments and to introduce only a
small number of model parameters. A set of values for these parameters
is an important result which is supported by new measurements for
standard cell blocks.


             DATE:    MONDAY, November 16, 1992

             TIME:    10:30 A.M. SEMINAR

             LOCATION:   Anneberg 221

             HOST:       Prof. Alice C. Parker
                         213 740-4476