🚀 go-pugleaf

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In article <2480@sdcsvax.UCSD.EDU>, John B. Nagle writes:
>                                  Part of the problem is that the construction
> of a layered operating system requires suitable hardware for efficient 
> interaction between the layers.  Such hardware is not rare; most superminis
> and mainframes have it; but most microprocessors do not, partly because this
> issue cuts across the line between the processor and the memory management
> hardware, and for most microprocessors, these are on separate chips, and the
> chips are so designed that operation without an MMU is possible.

The 68020 added "CALLM" and "RTM" instructions that implement the same
kind of ring-crossing calls as the DG MV series (and Multics, though I
haven't worked with Multics so I could be misrepresenting their
hardware).  There is support in the 68020's MMU for "call gates" and
all the associated paraphanelia to make it work.  The MMU checks the
top 3 bits of all accesses to ensure that low-privileged rings cannot
access the memory addresses reserved for high-privileged rings, and 
the CPU run special cycles to tell the MMU when to change its privilege
level.

I have heard that this feature is being dropped from the 68030, which
integrates the CPU and MMU on one chip, because NOBODY USES IT.  Also,
the microcode to do it is complicated and it takes the chip designers
weeks to understand what it's supposed to do, then do it -- and they
can't afford the time in the Race to Market.

Part of the problem is that the stack format used is incompatible with
the original JSR and RTS instructions, so nobody compiles subroutines for
the new stack format, so nobody can compile calls that use them either.
Somebody who really wanted to use an expensive call instruction rather
than a simple JSR could change their compiler, but so far nobody has
wanted to :^).


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