🚀 go-pugleaf

 If you wish to be completely anonymous when replying to my article of four
 days ago "Verilog Won & VHDL Lost? -- You Be The Judge!" (Friday, May 12th)
 PLEASE still indicate your job, your company, whether you use Verilog or
 VHDL, why, for how long plus whatever opinions/impressions you have of the
 contest or the Verilog/VHDL wars.  I WON'T PUBLISH THIS INFORMATION but will
 use it for statistical reporting of opinions.  That is, you'll see in the
 follow-up article in "Integrated System Design" all sorts of reporting like:

  "X of the ABC based designers and Y of the JKL based designers reported:

     'blah, blah, most adamently blah!   Flimming-flam-flam and for
      blah I think blah.   Flamm  flim flop flooo blah goo blah blah
      flam.  Blah blah floo blah."

 (Please don't take replying anonymously lightly; it's far more powerful to
 reply publically.  So far with every opinion seen, I've found multiple
 people who will publically voice it.  There's just something about having
 engineers silenced by company politics and/or paranoid bosses' dictates that
 bothers me; hence I encourage these people to speak out statistically and
 with anonymity.  But, if you *can* reply openly, *please* do so.)

 To quote the original jury instructions: "in 150 words or less, send your
 thoughts to "jcooley@world.std.com".  Please don't send me "VHDL sucks." or
 "Verilog must die!!!" -- but personal experiences and/or observations that
 add to the discussion.  It's OK to have strong/violent opinions, just back
 them with something more than hot air.  (Since I don't want to be in the
 business of chasing down permissions, my *default* setting is *whatever* you
 send me is completely publishable.  If you wish to send me letters with a
 mix of publishable and non-publishable material CLEARLY indicate which is
 which.)"
                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

 P.S.  As always, please DO NOT copy any article back to me -- I *know* why
       you're replying!  :^)

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 3349 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."