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Article #2447Re: CRAY Question
From: Eugene D. Brooks III
Date: Fri, 02 May 1986 03:42
Date: Fri, 02 May 1986 03:42
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How can the Cray 1 M with slower memory be faster than a Cray 1 S for a special set of circumstances? The S has memory with a 4 clock cycle time. There are 16 banks. For stride 1 vector fetch the cycle time of the memory is 4 times faster than it really needs to be. Suppose you want good scalar performance? Suppose you want good performance on stride 4 vector fetch? Suppose you want good performance on stride 2 vector fetch? (in this case you only need 8 banks) How can a Cray 1 M be as fast? Suppose your application is stride 1 vector fetch and 99.99% vectorized. Even if the mos ram is 4 time slower, taking a 16 clock latency, the cpu will get full bandwidth. Suppose the slightly slower memory causes a missed chain slot, emabling parallel use of the adder and multiplier, to be hit. The machine with mos memory could be faster. This is of course for very special circumstances and do not look for faster performance on average. High scalar speed is where it at! Eugene
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Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.3 4.3bsd-beta 6/6/85; site lll-crg.ARpA Path: arc1-ca.pugleaf.net!utzoo!watmath!clyde!burl!ulysses!bellcore!decvax!ittatc!dcdwest!sdcsvax!ucbvax!ucdavis!lll-lcc!lll-crg!brooks From: brooks@lll-crg.ARpA (Eugene D. Brooks III) Newsgroups: net.arch Subject: Re: CRAY Question Message-ID: <1417@lll-crg.ARpA> Date: Thu, 1-May-86 23:42:11 EDT Article-I.D.: lll-crg.1417 Posted: Thu May 1 23:42:11 1986 Date-Received: Sun, 4-May-86 04:27:13 EDT References: <905@harvard.UUCP> Reply-To: brooks@lll-crg.UUCP (Eugene D. Brooks III) Distribution: net Organization: Lawrence Livermore Labs, CRG Group Lines: 19