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In article <1363@unc.unc.UUCP> hedlund@unc.UUCP (Kye Hedlund) writes:
>BUT, a 68010 is about 0.4 mips @ 10MHz, and a 68020 is about 1.5mips @
>16.67MHz (measured on SUN workstations running C under 4.2 BSD).
>This gives 0.040 mips/MHz for the 68010 and 0.091 mips/MHz for the 68020
>and suggests that there is better than 2:1 architectural and implementation
>advantage for the 68020 independent of the circuit technology.

   Your point that the mips/Mhz rate is a slightly accurate method of
measuring architectural efficiency is somewhat valid, but it must be 
pointed out that there is no good definition of either the MIPS or the
MHz rate.  Assuming that MIPS measures the average execution speed of
the average instruction ( and who says what is average? ), and MHz measures
clock cycle time, all you are actually measuring is the number of clock
cycles per instruction.  I have a computer that runs at 200 MIPS, and
executes one instruction per cycle.  However, because it only has one
instruction, it is not very efficient, although its specs look great.
In addition, you can use some Intelling, and tinker with your MIPS and MHz
rates.  By the way, what is a MHz rate?  Do you mean the number of cycles
per millionth of a second, and if so, do you include wait cycles and 
feed/refresh cycles?  The ratio of two meaningless numbers produces a
number which is still pretty meaningless.

-- 
-------
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Scott Dorsey       " If value corrupts
kaptain_kludge         then absolute value corrupts absolutely"

ICS Programming Lab (Where old terminals go to die), Rich 110,
Georgia Institute of Technology, Box 36681, Atlanta, Georgia 30332
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