🚀 go-pugleaf

>It was always
>my feelings that, if a CPU manufacturer were to write the language compilers
>first, THEN generate a CPU design to run it, we'd all be alot happier.  Yes,
>that sounds like a CISC design. ...

On the contrary: one aspect of RISC design consists of taking a set of
instructions that can be easily generated by one *or more* compilers
and implementing those instructions in hardware.  Designing a
compiler/optimizer for a CISC is much more complicated in some ways,
because each instruction may have many side effects, and there may be
many ways to accomplish a function.

I think you'll find that most CISC machines provide HLL-like
instructions which are suitable only for a single language.  Take a
DO-loop type instruction, for example.  The instruction might be quite
well suited to Fortran66, but unusable for Fortran 77, because of the
difference in the specifications of the trip count for the loops.  So
providing the instruction hasn't gained you much compared to
synthesizing it from simpler instructions (except in special cases,
such as benchmarking).  And it has probably hurt you because you could
have used the control store space (or hardwired logic area) to
implement some function more universally useful.

The IBM 801 architecture is an example of an architecture designed in
concert with a compiler.  The targetable 801 compiler was used to
generate code for some System/370 benchmarks, and the resulting code
ran 50% faster than the best code turned out by previous 370
compilers.  What's more, the resulting code used only a small subset of
the 370 instruction set.

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{cbosgd|ihnp4|pyramid|sdcsvax}!gould9!rb-dc1!silbey

Alex Silbey
Gould Inc., Computer Systems Division
15378 Avenue of Science
Rancho Bernardo, CA 92128
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{cbosgd|ihnp4|pyramid|sdcsvax}!gould9!rb-dc1!silbey

Alex Silbey
Gould Inc., Computer Systems Division
15378 Avenue of Science
Rancho Bernardo, CA 92128