🚀 go-pugleaf

In article <299@vaxb.calgary.UUCP> radford@calgary.UUCP (Radford Neal) writes:
>On RISC machines with delayed branches, who does the instruction
>rearrangement that tries to put useful instructions after the branch?
>Obvious possibilities are the assembler or the compiler. Does anyone
>know whether the compiler can do a significantly better job than 
>the assembler? (I'm assuming the compiler generates assembler code.)

1) Ours is in the assembler, and I think most others are, also.  I haven't
seen one that was in the compiler; maybe others have and would say so.

2) Our assembler does a lot of code selection itself to make life saner
for the compilers, i.e.,  load immediate reg,value can be 1 or 2 instructions,
and multiply by constant yields all sorts of sequences.
Pipeline reorganization naturally happens after such expansions.

3) It's possible that compilers might do it better; however, I don't see much
evidence of this [and I've looked at many 1000s of lines of dis-assembled code]:
Either:
	a) The reorganizer already fills the branch delay slot.
	b) The branch delay is there, and there's nothing anyone could 
	conceivably do about it.
	c) A modest smartening of the reorganizer would get rid of it,
	perhaps with also passing a little more information from earlier passes.
Most are in a) or b), and my gut feeling [no data] is that compilers can't
get much of c) that the assembler can't.
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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