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Article #2775Re: VERY LARGE main memories
From: Jonathan Hue
Date: Wed, 03 Sep 1986 09:39
Date: Wed, 03 Sep 1986 09:39
20 lines
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1519 bytes
In article <145@mn-at1.UUCP>, alan@mn-at1.UUCP (Alan Klietz) writes: > If you use DRAMs you have access times on the order of 50-200ns. That is > enough time for fast ECL-type logic to do plenty of decoding. I don't design with ECL, but just the buffers to go to/from TTL levels are going to be way slower than the FAST (that's right, Fast Advanced Schottky TTL) 74xx series stuff from Fairchild. With gate delays around 2ns, and 256K DRAMs at around 150ns, you have plenty of time to decode address lines. Heck you can just cram your decoder into a 20R8 PAL (I think it will fit) and the new ones are 15ns up to three gates deep. Of course, bipolar SRAMS with 3ns access times are another story... "If we did it like everyone else, Jonathan Hue what would distinguish us from Via Visuals Inc. every other company in Silicon Valley?" sun!sunncal\ >!leadsv!msunix!jon "A profit?" amdcad!cae780/
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Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: arc1-ca.pugleaf.net!utzoo!mnetor!seismo!nbires!hao!hplabs!oliveb!glacier!decwrl!amdcad!cae780!leadsv!msunix!jon From: jon@msunix.UUCP (Jonathan Hue) Newsgroups: net.arch Subject: Re: VERY LARGE main memories Message-ID: <250@msunix.UUCP> Date: Wed, 3-Sep-86 05:39:21 EDT Article-I.D.: msunix.250 Posted: Wed Sep 3 05:39:21 1986 Date-Received: Mon, 8-Sep-86 23:35:24 EDT References: <2017@sdcsvax.UUCP> <884@gilbbs.UUCP> <145@mn-at1.UUCP> Organization: Via Visuals Inc. Lines: 20 Keywords: memory size Summary: ECL!?!!