🚀 go-pugleaf

In article <12930@amdcad.UUCP>, philip@amdcad.UUCP (Philip Freidin) writes:
> do word select) you have 32 address select lines coming into the second
> level, address and address complement. each of these must drive 32k and
> gates!  I dont know of any logic familly with a drive capability to support
> that type of load. Your typical ttl has a drive capability of from 10 to 20
> loads.  Also, another fly in your fast decode ointment is that the way and
> gates are implemented in many logic families precludes building a 16 input
> and gate as a single level. Cmos is limited to about 4 levels, and TTL and
> ECL have similar limits. To build bigger and gates, you end up with a tree
> structure inside your and gate.

Most people don't worry about the decoders inside DRAMs, but just what the
DRAM looks like from the pins (timing, loads, etc).  As a crude example,
suppose you have a VME bus board with 100 in^2 and the P1 and P2 connectors.
You are using 256K DRAMs and can fit 4Mb on each board.  A1 thru A18 form the
row and column address.  That leaves A19 thru A23.  A19 thru A21 can be the
inputs to a 74AS138, and A22 and A23 can be the enables for the AS138 (it has
two low enables, and one high).  To put 16Mb in this system, you only need
one more gate to enable the AS138 when both A22 and A23 are high.

Okay, now add the P3 connector, 1Mb DRAMs, and twice as much real estate,
so you can put 32Mb on a board.  A2 thru A21 form the row and column
address, A22 thru A24 go into an AS138, and A25 thru A31 go into a
74AS688.  The AS688 can be used as an address comparator, and is nice
because you can stick eight address jumpers next to it to set the board's
base address.  The AS688 has an eight input gate in it, as do a lot
of the AS67x and AS68x parts.  The output of the AS688 along with
A1 control what the board puts on the bus.

You can address 4Gb with this scheme, and none of this looks much like a tree.
And there is a part here that has an eight input gate.  Add 8 more address
lines, another AS688, and you've got 1Tb.  This wouldn't be any slower to
access than the 24 bit example.  The point here is that you don't have to
design to decode n address pins into 2^n signals.  Your DRAMS take care of
18 or 20 of them, and you only need to decode as many as you have banks of
memory on a board.  The other address lines need only form a board select
 - one output only.



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