🚀 go-pugleaf

In article <8546@duke.duke.UUCP>, Stephen R. Tate (srt@duke.UUCP) writes:

>> [ comments by Philip Freidin on decoder tree structure deleted -- S. Rice]
> 
> First off, I was talking about decoding *bank* addresses, not individual
> word addresses.  . . .  Now that's only 8 bits for a bank address, and I
> have seen 8 input NAND gates.  (7430 or something like that....)  . . .

If you're going to design large memories, decode them *fast*.  Delays for
a 74AS30 are 5 ns max over temperature and +/- 10% Vcc (but 50 pf/500 Ohm
load).  Fanning out to 16 gates will push this out a bit (but not much).

> . . .  Each of these bank
> address lines need only drive one input per bank (32 chips), which means
> that they only have to drive 256 inputs.  Much less than your 32k figure,
> but still unreasonable.  Obviously, the address lines need to be buffered.
> Using TTL with a fanout of, say, 16, you only need one level of buffering
> (since 16*16 = 256).  Now you're three levels deep for a propogation delay
> of about 40-50ns.  Still not a terribly unreasonable time.

With currently-available logic, you should be able to go 3 levels in not much
more than 15 ns (oh, Lattice, where are those 10 ns GALs??).

> . . .
> Incidentally, CMOS has a *huge* fanout.  That is, CMOS outputs to CMOS
> inputs (no mixing).

CMOS has a huge fanout at DC. . .  As you try to do things fast, the
capacitive loading of the inputs becomes the dominant factor.  If you hang
a whole bunch of inputs on one CMOS output, the rise and fall times
become seriously degraded.  Some of the newer CMOS is quite capable,
though -- output drive capabilities that equal or exceed those of most
bipolar circuits.

					Steve Rice

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