🚀 go-pugleaf

In article <5100133@ccvaxa> aglew@ccvaxa.UUCP writes:
>
>There has been some discussion of delayed branches in this newsgroup;
>can anybody say anything useful about delayed load/stores? Ie. memory
>access functions that are defined to work the same way as delayed
>branches, not to take effect until after a few more instructions.
>
The benefit of such an approach is similar to that of delayed 
branches.  In a pipelined processor the result of an operation is not
available immediately so if the next instruction in the pipe requires the
result then the pipeline must be stopped until the result is ready.  This
interlock logic tends to significantly complicate the design of the CPU
and slows down execution times.  Performance of pipelined processors can be
improved by generating code that does not generate data dependent pipeline
interlocks.  Presumably microprocessors without pipeline interlocks have
delayed stores as well as delayed branches and for the same reason.

An even thornier problem arises if you allow self modifying code to be run
on your machine. i.e. You build a real Von Neuman machine.  The problem of
detecting stores into the instruction stream of  a pipelined processor is
even more difficult than detecting data interdependencies.  On the Amdahl
470 v8 (the pipelined processor that I am most familiar with) the attempt
is not even made to detect stores into instructions that are already in
execution.  All that they try to do is see if a store is "close" in  which
case the entire pipeline is flushed and serialized.
	
	Illigitimi non carborundum
		Hank Cohen