🚀 go-pugleaf

The table below is a reorganization of the following table.

				Relative Performance

processor	80286	80386	68000	68020	68020	32032	32100	32100
cache (MHz)	(10)	(16)	(8)	N (16)	C (16)	(10)	N (18)	C (18)

string search	1.37	1.00	3.85	2.25	1.08	3.51	4.71	1.89
bit manipulate	5.52	2.09	5.91	2.25	1.00	5.29	3.58	1.74
linked list	3.08	1.70	4.11	1.79	1.00	2.90	2.36	1.28
quicksort	4.07	2.49	4.39	2.05	1.00	3.12	3.12	1.32
matrix trans	6.42	2.05	5.49	1.58	1.00	4.33	3.04	1.47

average		4.09	1.87	4.75	1.98	1.02	3.83	3.36	1.54

In article <322@oblio.UUCP> paf@oblio.UUCP (Paul Fronberg) writes:
)In the August issue of IEEE Micro there is a very interesting article
)concerning benchmarking 32-bit microprocessors. The following table is
)abstracted from page 57. Numbers are time in seconds. (N=no cache enabled;
)C=cache enabled). This table reflects the results for dynamic memory.
)
)	 MHz	  E	  F	 H	  I	  K
)80286	(10)	 4.89	13.63	6.59	11.20	19.39
)80386	(16)	 3.57	 5.16	3.63	 6.86	 6.20
)68000	(8)	13.73	14.61	8.79	12.08	16.59
)68020 N	(16)	 8.02	 5.55	3.84	 5.65	 4.78
)68020 C (16)	 3.84	 2.47	2.14	 2.75	 3.02
)32032	(10)	12.52	13.07	6.21	 8.57	13.07
)32100 N (18)	16.81	 8.84	5.05	 8.57	 9.17
)32100 C (18)	 6.75	 4.29	2.74	 3.63	 4.45
)
)Benchmarks are EDN 16 benchmarks modified for 32 bits. The benchmarks were
)coded in assembly code for each processor.
)
)The following EDN programs were used.
)
)Test E is a character-string search routine.
)
)Test F is a bit test, set, and reset routine.
)
)Test H is a linked-list insertion routine.
)
)Test I is a quicksort routine.
)
)Test K is a bit-matrix transposition routine.


-- 
  Lawrence Crowl		716-275-5766	University of Rochester
			crowl@rochester.arpa	Computer Science Department
 ...!{allegra,decvax,seismo}!rochester!crowl	Rochester, New York,  14627