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Article #3042

Re: paging and loading

#3042
From: Josh Knight
Date: Fri, 17 Oct 1986 18:17
32 lines
2439 bytes
In article <7232@utzoo.UUCP> henry@utzoo.UUCP (Henry Spencer) writes:
>> ... The IBM 3090 has already shown an example of a
>> system where it is faster to page synchronously rather than context switch,
>> in which case your CPU *is* idle while paging - and these are likely to
>> become more common. ...
>
>Ah, but what device are they paging from?  If I remember it correctly --
>I'm not sure of this -- the 3090 is paging out of ordinary RAM, which they
>would have preferred to make directly addressable except that they are
>constrained by backward compatibility and not enough address bits.  This
>is a kludge, not something that is likely to become widespread.

What IBM prefers to do is a difficult thing to determine (wish I
could ;-).  It is true that the expanded storage announced for the
3090 is "ordinary RAM".  However, it is not necessarily true that one
would prefer to have real memory instead of a fast page addressable
store.  The address bits required to maintain the latter (only page 
addresses are maintained) are fewer and one does not have to maintain
whatever protection mechanisms (in the case of the IBM 370 architecture
storage protect keys) are provided for "main storage".   In addition,
page stores could have different porting and provide access to multiple
processors and/or I/O servers with less overhead.  These latter features
are not supported by the 3090 expanded storage, but other systems might
choose page addressable stores over byte addressable stores for these
reassons.
 
Of course, I'm speaking only for myself, not my employer.
 
-- 

	Josh Knight, IBM T.J. Watson Research
 josh@ibm.com, josh@yktvmh.bitnet,  ...!philabs!polaris!josh
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Message-ID: <752@polaris.UUCP>
Path: arc1-ca.pugleaf.net!utzoo!watmath!clyde!caip!elbereth!rutgers!sri-spam!nike!cit-vax!ll-xn!adelie!axiom!linus!philabs!polaris!josh
References: <949@usl.UUCP> <5100148@ccvaxa> <7232@utzoo.UUCP>

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Path: arc1-ca.pugleaf.net!utzoo!watmath!clyde!caip!elbereth!rutgers!sri-spam!nike!cit-vax!ll-xn!adelie!axiom!linus!philabs!polaris!josh
From: josh@polaris.UUCP (Josh Knight)
Newsgroups: net.arch
Subject: Re: paging and loading
Message-ID: <752@polaris.UUCP>
Date: Fri, 17-Oct-86 14:17:33 EDT
Article-I.D.: polaris.752
Posted: Fri Oct 17 14:17:33 1986
Date-Received: Tue, 21-Oct-86 21:21:31 EDT
References: <949@usl.UUCP> <5100148@ccvaxa> <7232@utzoo.UUCP>
Reply-To: josh@polaris.UUCP (Josh Knight)
Organization: IBM Research, Yorktown Heights, N.Y.
Lines: 32
Keywords: paging, pages, memory, addressability
Summary: Page addressing and memory addressing are not the same