Nasty Instructions

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Article #3079

#3079

From: Hugh LaMaster
Date: Mon, 27 Oct 1986 22:52

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A question for hardware designers and computer architects on the net:

What instructions actually slow a processor down?  While the RISC/CISC
debate has often focused on complexity, chip real estate, etc., there
seem to be cases where the existence of a particular instruction can
slow the processor because of pipelining considerations.  Complex
addressing modes are also a question:  Are there indirect or complex 
addressing modes whose implementation necessarily slows down direct 
loads and stores?  What is the best example of an existing CISC
machine which does not have any of these "unnecessary" architectural
features or instructions? 

   Hugh LaMaster, m/s 233-9,   UUCP:  {seismo,hplabs}!nike!pioneer!lamaster 
   NASA Ames Research Center   ARPA:  lamaster@ames-pioneer.arpa
   Moffett Field, CA 94035     ARPA:  lamaster%pioneer@ames.arpa
   Phone:  (415)694-6117       ARPA:  lamaster@ames.arc.nasa.gov

"He understood the difference between results and excuses."

("Any opinions expressed herein are solely the responsibility of the
author and do not represent the opinions of NASA or the U.S. Government")

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Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Path: arc1-ca.pugleaf.net!utzoo!mnetor!seismo!lll-crg!nike!lamaster
From: lamaster@nike.uucp (Hugh LaMaster)
Newsgroups: net.arch
Subject: Nasty Instructions
Message-ID: <704@nike.UUCP>
Date: Mon, 27-Oct-86 17:52:45 EST
Article-I.D.: nike.704
Posted: Mon Oct 27 17:52:45 1986
Date-Received: Mon, 27-Oct-86 23:21:52 EST
Sender: usenet@nike.UUCP
Reply-To: lamaster@pioneer.UUCP (Hugh LaMaster)
Distribution: na
Organization: NASA Ames Research Center, Moffett Field, Calif.
Lines: 22
Keywords: Pipelining