🚀 go-pugleaf

I'd like to thank those that responded to my original query.  I've tried
e-mailing thanks to all of you, but several were returned.

I'm under non-disclosure with both NCR and Intel, so I can't publish my
results.  I can say that I have found no gross errors on the part of
Intel in benchmarking their chip.  As far as Dhrystone's go, the tiny
model/large model/huge model modes don't seem to make a huge difference.
The overhead of Unix is somewhat evident, but if you'll think about it
their shouldn't be much overhead associated with Unix if the port is
done correctly and is tuned for running CPU benchmarks.

In pulling out logic analyzers and looking at the their system, it seems that
the biggest advantage of the I80386 is the 2 cycles necessary to go to memory.
The debate over whether systems will actually use cache capable of running
at 2 cycles has been much debated -- I can only say that if I didn't I would
attempt to at least use SCRAM's.  On-chip MMU's as a rule are very nice...I'd
much rather design a physical cache than a logical cache.  I'm glad that
both Intel and Motorola are now both using on-chip MMU's.

The one question I have remaining is how Intel plans to use the pipelining
feature (signal NA) of the I80386.  The statistical benchmarks that they show
assume that you will get a x% hit rate from the cache, and that y% of the
misses from the cache will pipelined.  Seems to me that you'd have to have
a crafty little piece(s) of hardware deciding whether to drive NA.  If anyone
knows, please post, I think it would be of general interest.
-- 

Mark Campbell    Phone: (803)-791-6697     E-Mail: !ncsu!ncrcae!sauron!campbell