🚀 go-pugleaf

> Does anyone out there have a list of references to articles on
> cache memories that they wouldn't mind sharing?

Alan Jay Smith of UC Berkeley compiled an extremely comprehensive
"Bibliography and Readings on CPU Cache Memories and Related Topics",
found in the Vol. 14, No. 1, January 1986 issue of Computer Architecture
News, an informal quarterly publication of the ACM Special Interest
Group on Computer Architecture (SIGARCH).  It contains approximately
400!!! references.

> What interests me most is work done on simple caches for multi-processors
> (so not the things that don't write through, and need funny memory
> boards that know their copy of a word is invalid, etc),
> and how they perform. The performance I'm most interested in is
> in keeping the bus free, not speeding up the processor.

Perhaps for a very immediate application it is best to stick to
write-thru caches for your multiprocessor, but you might look to
the IEEE P896 Futurebus for ways to build economical shared memory
multiprocessors with copy-back caches.  The Futurebus has explicit
support for caches called "three party transactions" that allow a
cache holding dirty data to dynamically disable the memory module
and respond in its place.  Memory modules are not burdened with special
requirements like valid bits.  The cache coherence specification,
P986.2, is now being written, and an informal description appeared
in the September 9 issue of Electronic Design.

/ nucsrl:net.arch / jack@mcvax.uucp (Jack Jansen) /  5:39 pm  Oct  1, 1986 /

>Does anyone out there have a list of references to articles on
>cache memories that they wouldn't mind sharing?
>What interests me most is work done on simple caches for multi-processors
>(so not the things that don't write through, and need funny memory
>boards that know their copy of a word is invalid, etc),

You might have a look at Kai Hwang & Faye Briggs book, "Computer Architecture
and Parallel Processing". It has an interesting section on multiprocessor
caches. I don't have my copy handy, but I remember that they give you a
reasonable number of references at the end of the chapter. Although, you
indicate that you are not too interested in algorithms that don't do write
through, the Hwang & Briggs book gives a really nice algorithm for a 
dynamic coherence check that does not require write through.

Another source of references would be Alan Jay Smith's article on cache
memories in the Sept. '82 issue of Computing Surveys.


>	Jack Jansen, jack@mcvax.UUCP
>	The shell is my oyster.

	Naim Abdullah
	Dept. of EECS
	Northwestern University
	ihnp4!nucsrl!naim

> 
> A couple of months ago, I asked this same question, and didn't
> get any answers. So, let's blame it to the holidays, and try
> again:
> 
> Does anyone out there have a list of references to articles on
> cache memories that they wouldn't mind sharing?
> What interests me most is work done on simple caches for multi-processors
> (so not the things that don't write through, and need funny memory
> boards that know their copy of a word is invalid, etc),
> and how they perform. The performance I'm most interested in is
> in keeping the bus free, not speeding up the processor.
> 
> As always, I'll summarize, if requested.
> -- 
> 	Jack Jansen, jack@mcvax.UUCP
> 	The shell is my oyster.

For those interested-- I have one of Alan J. Smith's cache bibliographies
that would make your head swim.  It is about 17 solid pages of references.
The note attached to my copy indicates that it was submitted to "Computer
Architecture News," although I don't know which issue it ended up in.
The latest references are for late 1985, so it should only be necessary
to check this year's issues.  I would suggest looking for this first, and
then if you are unsuccessful to contact Alan at UC-Berkeley.  I may have
his e-mail address around if you e-mail me.  In fact, if you really ask
nicely and promise to "reimburse" me, I could send off a copy.

	Mark Papamarcos
	Valid Logic
	hplabs!ridge!valid!markp