🚀 go-pugleaf

Notes on LSL:
	1) The LSL facility for UCDS seems to work acceptably
	   for poly-cell generation when all inputs (and outputs)
	   are used.
	2) When a pin is NOT used the "missing pin" diagnostic
	   is printed and the pin is skipped:
	      This is an incorrect action because when positional
	      notation is used, unused pins should be marked by
	      consecutive commas (essentially a null signal name).
	      FIX:
	      In ./cdm/L.c put a 'prs(",")' statement before
	      each 'missing(src)' call (and recompile).
	3) Some programs (notably those used by the WH EID for
	   test-vector generation of TTL) use keyword notation
	   rather than positional notation.  This requires that
	   each signal be assigned to the appropriate pin number
	   as follows: P4=SIGNAL3, which will assign pin 4 to
	   a signal by the name of "SIGNAL3".  This is as opposed
	   to the postional notation which would require only
	   the signal name.  I have added a '-k' option to
	   cdm -L which will use this notation rather than the
	   default.  It uses the absolute value of the pin number
	   (see below) since it is used only for wiring physical
	   packages (as opposed to poly-cells).
	4) Creating LSL for TTL (74xx00...) is not easy!!!
	   The problem is that the LSL program requires negative
	   pin numbers for the input pins.
	   a) If pin numbers are used in the schematic this will
	      make the schematic messy.
	   b) Wrap and Place may not like negative pin numbers?
	      (I haven't tried this)
	   c) The available libraries don't use this notation
	   d) Part of the LSL generation procedure uses the sort
	      program to order the pins.  If negative pin numbers
	      are used for the input pins, these will end up being
	      sorted by inverse absolute value (ie. if pins 2 and 9
	      are inputs, pin -9 will be defined before pin -2).
	      (The keyword notation gets around this problem.)
	   FIX: ???
	      i) make the cdm program smart enough to translate positive
		 numbers to negative.
		 COUNTERPROBLEM: the polycells use +1 and -1 on the same
		 		 device!
	      ii) modify cdm -L to extract I/O information from the
		 plh library.
	      iii) always use keyword notation for TTL descriptions, and
		 use pin names (not numbers) for the drawing.  Then either
		 modify wrap and place to accept negative numbers and
		 change the pins library, or make two separate libraries one
		 for wrap and one for LSL.
	      iv) to use positional notation, create an LSL library that
		 has dummy pin numbers designed to make the pin numbering
		 come out the same as the LSL parts library that you are using.
		 (eg. if your LSL library expects input pins 3, 1, and 6
		 in that order for the A inputs,
		 the real assignments might be:
		 .tp A1 1
		 .tp A2 3
		 .tp A3 6
		 but the LSL .tp line would be:
		 .tp A1 -2
		 .tp A2 -3 (note that after sorting, this will come out first)
		 .tp A3 -1 (note that after sorting, this will come out last)
	      v) OTHER???? HELP!!!!