🚀 go-pugleaf

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I have some questions about the NS32032's addressing modes:

	What does the Scaled Index addressing option do when applied
	to a Register addressing mode?  In other words, what does
	something like "MOVW R1[R3:B],R0" do?  

	What results from doing something like "ADDR R1,R0"?

I do not have a machine to try these out on, otherwise I would.  I am
designing a high level assembly language for the 320xx family and I need
to know what is meant by the above constructions.

In the documentation I have (see below) nothing is said about the legality
of these constructions.  It does say that Scaled Index may not be applied
to the Immediate addressing mode or another Scaled Index addressing mode.
I understand how Scaled Index works for the other combinations.  I am
surprised that if the above constructions are meaningless, it is not stated
so in the documentation.

Admittedly, most of my documentation is old.  More current manuals may
address this issue (sorry about the pun...).  I have these documents:

	NS16000 Microprocessor Family Reprint of Technical Articles (1980)

	NS16000 Programmers's Reference Manual
		(Feb. 1982)

	NS32032-6,NS32032-10 High-Performance Microprocessors
		(Preliminary Data Sheet, Feb. 1984)

	NS16032 High-Performance Microprocessor
		(Preliminary Data Sheet, Apr. 1982)

	NS16201 Timing Control Unit (TCU)
		(Preliminary Data Sheet, June 7, 1981, Rev. H)

	NS16202 Interrupt Control Unit
		(Preliminary Data Sheet, Oct. 1982)

	NS16082 Memory Management Unit (MMU)
		(Preliminary Data Sheet, Mar, 1982)


					Thanks,
					David Sowell


David C Sowell
Georgia Insitute of Technology, Atlanta Georgia, 30332
...!{akgua,allegra,amd,hplabs,ihnp4,seismo,ut-ngp}!gatech!gitpyr!dcs