🚀 go-pugleaf

In article <446@terak.UUCP> doug@terak.UUCP (Doug Pardee) writes, quotes:
>> ...  With a 10 Mhz 32032 *or* 32016 one can get real memory response times
>> of 200ns...
>
>... At 10 Mhz, each clock is 100 ns... the shortest possible bus cycle on a
>32xxx is 4 clocks.  That's 400 ns.  If you have an MMU, it's 5 clocks, or 500>ns.

I don't think National literature backs either of you, however, these numbers
were heard over the phone from National:

		byte	align	unalign	align	unalign
			 word	 word	 double	 double
				 or
				aligned
				 double

'016		   3	   3	   7	   7	  11
'016+MMU	   4	   4	   9	   9	  14
'032		   3	   3	   3	   3	   7
'032+MMU	   4	   4	   4	   4	   9

These numbers represent operand fetch times, and do not include processor
overhead.  Note that multiple CPU's *could* operate the bus at these speeds
if driven lock-step from a multi-phase clock.  This may be a nit-pick, but
bus cycle time is not instruction sequence time.
-- 
:::::: Jan Steinman		Box 1000, MS 61-161	(w)503/685-2843 ::::::
:::::: tektronix!tekecs!jans	Wilsonville, OR 97070	(h)503/657-7703 ::::::