🚀 go-pugleaf

The figures reproduced below were obtained by "fudging" out the last
clock cycle of an operand access (T4).  This is the "wind-down" cycle,
where the various control lines are released.  Notice that while a
single-cycle is shown to need 4 clocks w/MMU, a double-cycle needs
9 and a triple-cycle needs 14 -- all but the last cycle are shown at
the full 5 clocks.

The figures below represent the CPU's view of bus timing, since it
has all of the operand data it needs without waiting for the wind-down
clock cycle to complete.  But it still cannot access the bus again
until that clock cycle has finished.

These figures are an accurate picture of operand access time on an
otherwise idle memory bus.  They don't represent end-to-end memory
bus cycle times.

> I don't think National literature backs either of you, however, these numbers
> were heard over the phone from National:
> 
> 		byte	align	unalign	align	unalign
> 			 word	 word	 double	 double
> 				 or
> 				aligned
> 				 double
> 
> '016		   3	   3	   7	   7	  11
> '016+MMU	   4	   4	   9	   9	  14
> '032		   3	   3	   3	   3	   7
> '032+MMU	   4	   4	   4	   4	   9
-- 
Doug Pardee -- Terak Corp. -- !{hao,ihnp4,decvax}!noao!terak!doug