Re: Questions about Scaled Index addressing mode

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1 total messages Started by Mike Lesher Sat, 09 Mar 1985 21:02

#189

Author: Mike Lesher
Date: Sat, 09 Mar 1985 21:02

31 lines
1606 bytes

[Row, row, row your bits, gently down the stream...]

In article <> dcs@gitpyr.UUCP (David Sowell) writes:
>------
>
>I have some questions about the NS32032's addressing modes:
>
>	What does the Scaled Index addressing option do when applied
>	to a Register addressing mode?  In other words, what does
>	something like "MOVW R1[R3:B],R0" do?  
>
>	What results from doing something like "ADDR R1,R0"?
>
>I do not have a machine to try these out on, otherwise I would.  I am
>designing a high level assembly language for the 320xx family and I need
>to know what is meant by the above constructions.
>
>
>David C Sowell
>Georgia Insitute of Technology, Atlanta Georgia, 30332
>...!{akgua,allegra,amd,hplabs,ihnp4,seismo,ut-ngp}!gatech!gitpyr!dcs

I have tried these instruction on our system an found:
	MOVW R1[R3:B],R0 = MOVW @(R1+R2), R0
	ADDR R1,R0 = MOVD R1, R0

I hope this answers your questions.

Mike Lesher
Burroughs ASG, San Diego, CA.
(..!bmcg!mikel)

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