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Article #772

Re: OS0 Level II

#772
From: Peter C. Dibble
Date: Thu, 21 Aug 1986 14:32
34 lines
2424 bytes
In article <316@vaxb.calgary.UUCP>, ingoldsby@calgary.UUCP (Terry Ingoldsby) writes:
> Specifically, I would like to know how Level II accomplishes
> the extended address space.  Are programs limited to 64K?  Is data limited
> to 64K?  Any info would be most appreciated.

Each process under Level Two can have ALMOST 64k.  It divides that space 
between code and data however it likes.  Level Two requires memory management
hardware, a DAT (Dynamic Address Translator).  The DAT maps enough pages to
make up a 64K into the  address space of each process.  On the CoCo, with
8K pages, that is eight pages per address space.  If the process doesn't need
a full 64K it gets copies of a special dead page in the unused part of the 
range.

If a process needs more than 64K it can do a number of complicated things that
aren't actually much worse than what PC users do with segments.  You can move
data between address spaces, or simply start several processes to get access to
more than 64K.   The easiest way to share data amoung processes is with a data
modules mapped into all the address spaces.

The most common problem with Level One programs running on Level Two is
references to addresses that aren't in your address space.  

Brief toot on my horn: I cover Level Two very carefully
in my part of "The Complete Rainbow Guide to OS-9."  Tandy
has been selling it for some time.  Do they know that they've been explaining
the advantages of Level Two to CoCo owners?

Peter Dibble

oops:  I said ALMOST 64K...  Most hardware doesn't switch DAT registers when
there is a hardware or software interrupt.  Unless the hardware does this 
and provides memory-to-memory DMA, about 256 bytes of OS-9 have to go at the
top of each address space to provide interrupt vectors and some services
that can't dissappear each time the address space is munged with.
Technical Details
Message-ID: <20312@rochester.ARPA>
Path: arc1-ca.pugleaf.net!utzoo!mnetor!seismo!rochester!dibble
References: <316@vaxb.calgary.UUCP>

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Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Path: arc1-ca.pugleaf.net!utzoo!mnetor!seismo!rochester!dibble
From: dibble@rochester.ARPA (Peter C. Dibble)
Newsgroups: net.micro.6809
Subject: Re: OS0 Level II
Message-ID: <20312@rochester.ARPA>
Date: Thu, 21-Aug-86 10:32:18 EDT
Article-I.D.: rocheste.20312
Posted: Thu Aug 21 10:32:18 1986
Date-Received: Thu, 21-Aug-86 21:14:23 EDT
References: <316@vaxb.calgary.UUCP>
Organization: U of Rochester, CS Dept., Rochester, NY
Lines: 34
Keywords: Code size?
Summary: Level II Memory Mgmt