🚀 go-pugleaf

I'm a little disturbed by the reports of the new 68030's on-chip
cache for data accesses.  I'm concerned about accesses to I/O devices,
which are (by necessity) memory-mapped in 68xxx machines.

Problem #1: if the chip decides to cache the value read from an
I/O device status register, subsequent reads will not produce the
current contents of that register.

This problem also applies to shared variables in a multi-CPU, shared
memory machine (which is supposedly a design target for Motorola ...
remember TAS, CAS and them other funny instructions?)

Problem #2: the caches are apparently built to slurp in 16 bytes
around any referenced location, on the theory that adjacent words
may be required soon.  (While this makes good sense for instructions,
I'm not at all sure that I buy it for data.)  This is *extremely
dangerous* for I/O devices, as adjacent locations (1) may not exist,
or (2) may have some active response to being read ... e.g. clearing
an interrupt request.

Now I assume that the 68030 group are not fools, and that they
thought about this problem.  What did they do about it?  Is there
a mechanism for keeping certain (ranges of?) addresses from being
cached?  How do they expect software to handle shared variables?

Looking forward to enlightenment...

				tom lane
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