🚀 go-pugleaf

Don't bother "poke-blasting" the memory controller ("MMU") address
space.  There's nothing interesting there.  If you don't believe me,
then go ahead.

The 68000 makes a bus request every 4 cycles.  This means that there are
3 other cycles available for doing stuff.  2 of these cycles are used for
video DMA.  1 more is used for disk DMA.

Now, it is NOT true that the 68000 makes a memory access every 4
cycles (I lied.)  The processor is given a window every 4 cycles,
and it is stopped if it makes a request that is out of line.  It
quickly falls back into step.  This means that the processor loses
cycles occasionally, but very occasionally.

(If you don't beleive me, go ahead: write some assembly language
benchmarks and count cycles.  THEN you can start talking numbers
about "occasionally".)

Multiport RAM on a consumer machine?  Yick.  How much does that COST?


-landon
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