Re: Bus contention

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Article #2367

#2367

From: jhs
Date: Mon, 03 Feb 1986 16:07

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COMPUTE! Magazine's "product description" of the 520ST, I believe in the
October, 1985 issue, described the CPU/DMA interface to memory.
What they described sounded like essentially a time-multiplexed form of
dual-porting: neither the CPU nor the DMA controller ever (much) has to wait
for memory access.  (They pointed out that because the 68000 accesses memory
asynchronously, it will OCCASIONALLY happen that it will have to wait, but
so rarely that you will never see it in terms of throughput.)

						-John Sangster
						jhs at mitre-bedford.arpa

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From: jhs@MITRE-BEDFORD.ARPA
Newsgroups: net.micro.atari
Subject: Re: Bus contention
Message-ID: <8602031607.AA14143@mitre-bedford.ARPA>
Date: Mon, 3-Feb-86 11:07:52 EST
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Posted: Mon Feb  3 11:07:52 1986
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