🚀 go-pugleaf

In article <162@puff.UUCP> scott@puff.UUCP (Scott Aschenbach) writes:
>In article <767@ark.UUCP>, gijs@ark.UUCP (Gijs Mos) writes:
>> In article <508@elmgate.UUCP> jdg@elmgate.UUCP writes:
>> ...
>> >If memory serves me correct the 68000 can not restart/resume a bus faulted
>> >instruction...
>...
>I though I heard of someone using pairs of 68000's before the 68010s
>came out.  One was set to run just a bit ahead of the other, so that
>the first faulted, and the second was in the state the first one should
>be in when it was restarted.

Close.  Actually, one of the processors is set-up as the "run" processor,
and the other as the "fault" processor.  The run processor executes all
normal program instructions, and has its bus cycles terminated with a
DTACK*.  If a bus cycle faults, the BERR* signal goes only to the fault
processor.  It then issues a "relinquish and retry" (BERR*, HALT*, BR*) to
the run processor which immediately terminates the "faulted" bus cycle,
saves the access address internally for later use, and issues a BG*.  The
fault processor, upon receipt of the BG*, issues BGACK*, and releases BERR*
and HALT*.  Then, with the aid of a little external glue (address latches,
etc), the fault processor fixes the memory image at the faulted address, and
releases the BGACK* line.  The run processor will rerun the faulted cycle
using the same address, data, control signals, etc.

Actually, with this method, even a very complex management scheme can be
designed.  And, with the price (1000 pc qtys) of 8 MHz 68K's being about
1/4 that of 68451 MMU's, the price *disadvantage* of using a fault processor
is almost non-existant.  (remember that all mapping circuitry will have
to be added).  Also, assuming the mapping can be made sufficiently fast, this
method has some neat advantages.
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Disclaimer:  The opinions expressed herein are all mine.  Motorola pays me
	     to think, but not to express corporate policy.
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Tom Johnson