🚀 go-pugleaf

> > >                                                 You could do
> > > the same with a 68000. With a couple of 35ns rams and some address
> > > decoding (to map them into memory) you can implement a similar type of
> > > .......
> > 
> > It's a nice idea in general . . . but not on the ST.  Address
> > timing is *so* critical that running the address lines through a
> > 35ns RAM would result in missing RAS and/or CAS windows on the
> > DRAMs.  Bad things happen.
> 
> By design, this can be a non-problem. Drams have three parts to each cycle:
> 
>    1) RAS/CAS precharge   -- Overlapped with end/begining of M68k cycle
>    2) RAS/Row address     -- taken from M68k address lines after AS asserted
>    3) CAS/Col address     -- taken from MMU result after delay from AS asserted
> 
> The delay from RAS to CAS required/accepted by most DRAMS is about the same
> is running the address lines thru a mapping ram or adder/comparator based mmu.
> Addresses and function codes precede AS by half a clock giving a little more
> head room.  RAS can be started without knowing if the translation will be
> valid, since witholding CAS is a refresh cycle.
> 
I hate to tell you folks, but Andy Bechtolsheim here at Sun has a patent 
(applied for and granted) on using the untranslated addresses as the 
RAS addresses and doing the MMU address translation before the column 
addresses are needed for CAS.  Sooner or later, it's going to cost some
competitors a WHOLE lot of money.
 
-- 
-Jim Ludemann

"186,000 miles per second.  It's not just a good idea, it's the law."