🚀 go-pugleaf

The 3K resistor R32 is just a "pullup" resistor which puts a logic "1" on
the unused pin 1 of the 64K RAM chip.  If a 256K RAM is substituted as in the
Newell or similar upgrades, this pin becomes the 17th and 18th bits of the
address, since it, like the other 8 address lines, is multiplexed to get two
address bits per wire.  (The Phase 2 clock line is used to switch back and
forth between the two sets of 8 bits, or 9 bits if you have upgraded.)
Note that address bits are numbered 0 through 15 for the stock 800XL and so
presumably 0 through 17 for the 18 bits needed in the upgrade.

If you plugged in 256K RAMs and left the bit unchanged, it would make Bits
16 and 17 (the 17th and 18th bits) constantly "1", thus utilizing a particular
block of 64K bits in the RAM and leaving the others out of use.

If you hook a TTL logic gate to the IC (not 5V) end or R32 then that gate
takes control of the logic level and does whatever it feels like, hopefully
putting the other 3 64K blocks to good use.

If the TTL circuit driving the extra address input has its own internal pullup
resistor, then it would be best to remove the 3K resistor.  If the gate has
no internal pullup, then it should be connected to the resistor and the
resistor left in place.  That MAY explain the different approaches by
different upgrade designs.  On the other hand, typical TTL gates have enough
internal current sinking capability so that even one with an internal pullup
resistor shunting the 3K external one will work just fine if you leave the 3K
resistor in place.

I hope that clears up any question you have.

Incidentally, the logic board of the Newell (or other) upgrade has only to
"compute" the correct bit value for that one output at all times, in order to
make the upgrade work.  This means thinking up the right bit for each phase
of the Phase 2 clock, and of course taking into account whether or not the
ANTIC chip temporarily wants to do something, in which case it will assert
its HALT output line, telling the 6502 CPU to halt.  When that happens, the
upgrade logic has to say "hmm... ANTIC wants the memory.  What values does it
want for Bits 16 and 17".  That's where Newell assumed it would always want to
stay on the main memory segment in the 16-32K region.  He then suggested a
switch to let it follow the banked memory, which allows XLENT's Typesetter to
work.  The 130XE lets $D301 Bit 5 control this choice.  Newell's design will
turn out to be incompatible if anyone ever uses the 130XE capability of
dynamically changing this convention.  I have tried to urge Wes Newell to
redesign the board to follow the Atari 130XE convention more closely, but so
far to no avail.  I have proposed several variants of a scheme that would be
more compatible (David Young seems to agree on this), but so far have not
convinced Newell that it would be worth the effort to change the circuit.  If
a lot of other potential customers were to bug him about it, he might possibly
become convinced.

-John Sangster
jhs@mitre-bedford.arpa