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PRESENTS A COMPUTER ARCHITECTURE SEMINAR ON

Real Time Debuggers

with

P. Parkinson
Department of Electrical Engineering
University of Waterloo

DATE:          Monday, November 28, 1983 at 3:30 PM

ROOM:          MC 6091A

ABSTRACT

The debugging of real time systems  with  control  complexes
consisting  of  many  processors is a rather difficult task.
One of the most severe failures in such systems are  proces-
sor  crashes.   Available instrumentation does not satisfac-
torily support the debugging of infrequent crashes that only
occur in some field locations.  The design of an intelligent
bus tracer which builds up a  record  of  correct  processor
behavior  and  triggers  when it sees a deviationn from this
behavior is  presented.   The  tracer  relies  on  a  common
fault-tolerance  mechanism  (watchdog timer) to draw conclu-
sions about correct program behavior  and  exploits  a  fine
structuring of the processor address space.  Although origi-
nally developed for peripheral processors in large  telecom-
munications switching machines, it could be used in any oth-
er high availability systems  with  man-machine  interfaces,
suitable processors, and program execution patterns.

                     November 23, 1983