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Started by Richard Griffith
Tue, 27 Feb 1996 00:00
IC Design Seminar: Built in Self Test for High Perforamnce DSP DataPaths
Author: Richard Griffith
Date: Tue, 27 Feb 1996 00:00
Date: Tue, 27 Feb 1996 00:00
55 lines
2953 bytes
2953 bytes
Title: IC Design Seminar Built-In Self-Test
When: Friday March 1, at 1:30 in Room 3324 ME
Where: CARLETON UNIVERSITY, ELECTRONICS DEPARTMENT
Info also at <http://www.doe.carleton.ca/doe/seminars/index.html>
Presented by the Department of Electronics, Carleton University
Sooner or later, often at their first paying design job, board, those
connected with IC design will ifind out about test costs. They are
always significant, and can easily exceed all other production costs
for a chip, especially if poorly implemented.
There are two general ways to test a digital IC:
One is to use many many test vectors and a $5,000,000 tester. This is
expensive.
Another is to let the IC test itself. This can reduce the tester cost
to next to nothing, but it may -add 20% to the chip area. This is
expensive.
There can be another way!
Built-In Self Test for High Performance DSP DataPaths Dr. Saman
M.I. Adham Design For Testability Advisor, Northern Telcom Fri
March 1, at 1:30 in Room 3324 ME
Traditional Built-In Self Test (BIST) techniques uses additional
circuit hardware to generate input the test-pattern and also
to compress the output responses into a short signature which
can be checked for correctness. Even though these structures
can share some of the circuits registers, they present a high
area overhead and have significant performance degradation due
to the added circuitry.
This talk presents a novel BIST technique that employs the functions
used in the DSP data path to generate test patterns and compress
responses without adding external structures. The basic method will be
described. Then the testability properties of a special DSP datapath
(Integrator) will be analyzed and design modifications will be
introduced to improve the fault detection and pattern generation
capabilities of the datapath.
Dr. Adham is a obtained his Ph.D. at Queens working in digital
testing and testability. He is now "Design For Testability
Advisor" in the Telecom Microelectronics Center at Northern
Telcom. He is heavily involved with present and future testing
methodologies for Northern.
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